1. Field of the Invention
The present invention relates to package structures and fabrication methods thereof, and more particularly, to a package structure having a redistribution layer and a fabrication method thereof.
2. Description of Related Art
A redistribution layer changes original locations of I/O pads of a chip through wafer-level wiring and bumping processes so as to provide a preferred circuit configuration, thereby achieving a package structure having good electrical properties and good bonding strength.
FIG. 1A is a schematic cross-sectional view of a conventional package structure having a redistribution layer and FIG. 1B is a schematic upper view of the package structure. It should be noted that FIG. 1B only shows a portion of the redistribution layer of the package structure and omits conductive bumps 140.
Referring to FIGS. 1A and 1B, a packaging substrate is provided, which has a body 100 and a plurality of conductive pads 112 formed on the body 100. A surface passivation layer 110 is formed on the body 100 and a plurality of openings 114 are formed in the surface passivation layer 110 for exposing the conductive pads 112. Then, a second passivation layer 120 is formed on the surface passivation layer 110 and the conductive pads 112, and a plurality of first openings 122 are formed in the second passivation layer 120 for exposing the conductive pads 112. Thereafter, a plurality of conductive vias 124 are formed in the first openings 122 of the second passivation layer 120, and a plurality of circuits 126 are formed on the second passivation layer 120 and electrically connected to the conductive vias 124. Therein, the circuits 126 have a plurality of electrical contacts 128 formed at ends thereof. Then, a first passivation layer 130 is formed on the second passivation layer 120, the circuits 126 and the electrical contacts 128, and a plurality of openings 132 are formed in the first passivation layer 130 for exposing the electrical contacts 128. Thereafter, a plurality of conductive elements 134 are formed in the openings 132 of the first passivation layer 130 and electrically connected to the electrical contacts 128. Subsequently, a plurality of conductive bumps 140 are formed on the conductive elements 134.
However, along with the multifunctional development of chips, to meet a greatly increased number of electrical contacts along with special requirements on resistors, inductors and capacitors, the redistribution layer is generally configured to have fine circuits that have a width less than 25 um. As such, during a chip bonding process, the circuits easily delaminate due to concentration of stresses on small contact areas between the circuits and the passivation layers. Further, in operation, the circuits may crack due to thermal stresses caused by temperature variations.
Therefore, how to overcome the above-described drawbacks has become urgent.